I. Field of the Invention
The present invention relates to electronic circuits. More particularly, the present invention relates to a novel and improved method and apparatus for controlling stages of a multi-stage circuit such as a sigma-delta analog-to-digital converter (xcexa3xcex94 ADC).
II. Description of the Related Art
An analog-to-digital converter (ADC) is an important component in many electronic circuits, and is especially important in digital communication systems. An ADC converts a continuous analog waveform into discrete samples at evenly spaced time intervals. The samples can subsequently be processed by other digital signal processing blocks to provide enhancement, compression, and/or error detection/correction of the sampled data. Exemplary applications which require ADCs are code division multiple access (CDMA) communication system and high-definition television (HDTV).
Some important performance parameters of an ADC include linearity, DC offset, and signal-to-noise ratio (SNR). Suboptimal values for these parameters can cause degradation in the performance of a communication system. Linearity relates to the difference between an actual transfer curve (digital output versus analog input) and the ideal transfer curve. For a flash ADC, good linearity is more difficult to obtain as the number of bits in the ADC increases. The DC offset can degrade the acquisition and tracking performance of phase locked loops and the error detection/correction capability of the decoder, such as the Viterbi decoder. SNR can affect the bit-error-rate (BER) performance of the communication system because the quantization and circuit noise from the ADC results in degradation of the sampled data.
In many communication systems, the received RF signal is downconverted to baseband before quantization. Typically, the received signal is downconverted from a RF frequency to an intermediate frequency (IF) in the first downconversion stage. The first downconversion allows the receiver to downconvert signals at various RF frequencies to a fixed IF frequency where signal processing can be performed. For example, the fixed IF frequency allows for a fixed bandpass filter, such as a surface acoustic wave (SAW) filter, to remove undesirable images and spurious responses from the IF signal before the second downconversion stage. The IF signal is then downconverted to baseband where sampling is performed to provide the digitized baseband samples.
In most communication applications, an ADC is required at the receiver. In some applications, the receiver is a commercial unit where cost and reliability are important design criteria because of the number of units produced. Furthermore, in some applications, such as a CDMA mobile communication system, power consumption is critical because of the remote/portable nature of the receiver.
In the prior art, a flash ADC or a successive approximation ADC is used to sample the received signal. In the flash ADC, the input signal is compared against L-1 reference voltages, which are generated by a resistive ladder, by L-1 comparators. Flash ADCs are bulky and consume large amount of power because L-1 comparators and L resistors are required. Furthermore, flash ADCs can have poor linearity and poor DC offset characteristics, if the L resistors in the resistive ladder are not matched. However, flash ADCs are popular because of their high speed.
Successive approximation ADCs are also often used in communication systems. These ADCs minimize complexity by performing approximations of the input signal over two or more stages. However, these ADCs can also exhibit the same poor linearity and poor DC offset characteristics as exhibited by the flash ADCs. Therefore, successive approximation ADCs as well as flash ADCs are not ideal candidates for use in many communication applications.
For some applications, improved data conversion performance can be achieved with a sigma-delta ADC (xcexa3xcex94 ADC).
The present invention provides a control mechanism that can be used to control a xcexa3xcex94 ADC to provide the required level of performance while reducing power consumption. The xcexa3xcex94 ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a xcexa3xcex94 ADC that is similar to the xcexa3xcex94 ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved.
An embodiment of the invention provides a data conversion circuit that includes a xcexa3xcex94 ADC coupled to a control circuit. The xcexa3xcex94 ADC includes a number of xcexa3xcex94 stages coupled in cascade that receives an input signal and provides data samples. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit couples to the detector stage(s), receives the detected signal, and provides conditioned samples. The signal processor couples to the conditioning circuit, receives the conditioned samples, and provides a control signal that selectively disables zero or more xcexa3xcex94 stages.
In an embodiment, at least one detector stage is implemented as a replica of one of the xcexa3xcex94 stages, and can be shrunken and/or biased with less current than the xcexa3xcex94 stage it replicates. The detected signal can be indicative of an amplitude of the input signal. The xcexa3xcex94 stages can be disabled based on the detected signal amplitude, and possibly based on the relative locations of the xcexa3xcex94 stages within the xcexa3xcex94 ADC. In a specific implementation, the xcexa3xcex94 ADC includes two fourth-order bandpass stages or two second-order lowpass stages. The data conversion circuit is advantageously used in a cellular (e.g., CDMA) receiver.
Another embodiment of the invention provides an electronic circuit that includes a multi-stage circuit coupled to a control circuit. The multi-stage circuit includes N signal stages coupled in a particular configuration (e.g., cascade, parallel, and others). The control circuit provides a control signal that selectively disables zero or more signal stages. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor that can be configured and operated as described above. The detector stage(s) can be implemented as replica(s) of the signal stage(s), and can be shrunken and/or biased with less current. The signal stages can be selectively disabled based on, for example, the amplitude of the input signal.
Yet another embodiment of the invention provides a control circuit for controlling a multi-stage circuit that includes a number of signal stages. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. At least one detector stage is implemented as a replica of one of the signal stages. The detector stage(s), conditioning circuit, and signal processor can be configured and operated as described above. The control circuit is advantageously used to control a xcexa3xcex94 ADC.
Yet another embodiment of the invention provides a method for controlling xcexa3xcex94 stages in a xcexa3xcex94 ADC. In accordance with the method, a characteristic of an ADC input signal is detected using one or more detector stages. At least one detector stage is implemented as a replica of one of the xcexa3xcex94 stages. The detected characteristic is compared against a comparison level. A control signal is generated based, in part, on the comparison. Zero or more xcexa3xcex94 stages are then selectively disabled in accordance with the control signal. The characteristic being detected can be an amplitude of the input signal, and the xcexa3xcex94 stages can be disabled based on the detected signal amplitude.